The need for chip-to-chip communication bandwidth has tracked the increasing circuit density and computational power of Integrated Circuit (IC) chips. This increased bandwidth has been provided both by increasing the number of chip-to-chip interconnections and by increasing the data rate per interconnection. In computer networks, bandwidth is often used as a synonym for data transfer rate-the amount of data that can be carried from one point to another in a given time period (usually a second). This kind of bandwidth is usually expressed in bits (of data) per second (bps). Occasionally, it's expressed as bytes per second (Bps).
Historically these chip-to-chip interconnections used electrical signaling and were provided at lowest cost by copper lines in printed circuit boards and by electrical card-to-card connectors. A large number of chips on multiple cards would be connected in this fashion.
Attempts made in the art to improve the chip-to-chip interconnections noted above using multiple connections to achieve desired bandwidth and throughput have all had their drawbacks.
As computers get faster, their net lengths limit the speed that signals can be transmitted. In the past, circuit cards have been connected to each other by right angle connectors. This arrangement forces the connectors of one circuit card to have its connectors along a first edge. This limitation forces all signals leaving the card to be carried to another card to connect to the first edge. Signal nets that start on the edge opposite to the connector first edge are forced to travel the full width of the circuit card thus making the net longer than it could be if it left the circuit card in the middle of the card. This longer net length thus limits the frequency at which the signals travel.
United States Patent Publication 20090004892 relates to a board connector module including a frame, accommodating an array of substantially-parallel signal leads (S) and ground leads (G) extending in a longitudinal direction (L). The frame includes edges extending substantially parallel to said leads and one or more transverse bars extending between said edges. The transverse bars of the frame may resist deflection or buckling of these leads and consequently allow for higher stack heights in mezzanine circuit board assemblies
U.S. Pat. No. 7,746,654 discloses a computer system is that includes a chassis, a system board coupled to the chassis, and a first connector extending from the system board at a first height and configured to receive a first printed circuit board, wherein the first printed circuit board is configured to be parallel to the system board when received by the first connector, and a second connector extending from the system board at a second height and configured to receive a second printed circuit board, wherein the second printed circuit board is configured to be parallel to the system board when received by the second connector. Other computer systems are provided that include a first mezzanine card and a second mezzanine card or multiple connectors and a plurality of printed circuit boards.
U.S. Pat. No. 7,429,176 discloses a modular board to board mezzanine ball grid array BGA connector including a plug, a receptacle and if needed an adapter. The plug and the receptacle can be made form the same base pieces to accommodate different stack heights. If a greater stack height is needed, spacers can be used in the plug and the receptacle to accommodate a greater selected stack height. The plug and the receptacle both include a base having interstitial diamond recesses in which the solder balls are disposed and in which one end of a contact is inserted. The plug may further include a plug cover that can be connected to the base, and the receptacle may include a receptacle cover that fits over its base.
U.S. Pat. No. 7,425,137 discloses a connector assembly for connecting first and second circuit boards in a substantially parallel relationship. It includes a first connector mateable to the first circuit board and a second connector mateable to the second circuit board. A third connector is mateable to the first and second connectors and is positioned therebetween. The third connector includes a wafer configured to provide a predetermined spacing between the first and second circuit boards.
U.S. Pat. No. 7,420,819 relates to an expanding high speed transport interface hardware method for motherboard. In the method, a mezzanine card is provided and the mezzanine card has a chip socket. An expanding hardware with high speed transport interface is installed in the chip socket of the mezzanine card. In addition, the mezzanine card is inserted into an idle CPU socket in a motherboard with plural CPU structure to make the mezzanine card electrically connect with the second CPU socket, so that the mezzanine card and the expanding hardware become components of the motherboard. Finally, the motherboard is activated to detect the mezzanine card and the expanding hardware and set the CPU bus as a data transmission path between the mezzanine card and the expanding hardware so as to expand interface hardware for the idle CPU socket.
U.S. Pat. No. 7,407,387 defines a modular board-to-board mezzanine ball grid array (BGA) connector which includes a plug, a receptacle and if needed an adapter. The plug and the receptacle can be made form the same base pieces to accommodate different stack heights. If a greater stack height is needed, spacers can be used in the plug and the receptacle to accommodate a greater selected stack height. The plug and the receptacle both include a base having interstitial diamond recesses in which the solder balls are disposed and in which one end of a contact is inserted.
U.S. Pat. No. 7,390,194 discloses reduced insertion force mezzanine connector is used to couple first and second circuit boards. In one embodiment a connector frame has a first end disposed against the first circuit board and defining a first wall, and an opposing second end disposed against the second circuit board and defining a second wall generally parallel with the first wall. A plurality of wafers is disposed. Each wafer has a first edge in sliding contact with the first wall and an opposing second edge in sliding contact with the second wall. A plurality of electrically conducting pathways extends along each wafer from the first edge to the second edge. A wafer guide structure defines a plurality of wafer-support aisles on the first and second walls for receiving the edges of the wafers to constrain the wafers with a fixed spacing and generally parallel alignment.
The patented prior art cited above has become less pertinent because, as computers have become faster, i.e., as communications data rates have increased, transmission line impedance discontinuities and frequency-dependent channel loss have limited the maximal electrical transmission distance. The result is that the net lengths of the computer limit the speed at which signals can be transmitted. These electrical signaling constraints have been mitigated, however, by: improved frequency-dependent and noise canceling signaling technology in the chip driver and receiver circuits; improved impedance matching design in the cards and connectors; and by using lower loss materials in the cards and connectors.
A more serious limit on the use of electrical chip-to-chip signaling has been the lack of a sufficiently reliable, separable and dense electrical card-to-card connection technology. As a result recent large-scale computing systems have trended towards signaling electrically over the largest possible circuit card, and using dense but expensive optical interconnections between circuit cards.
Since optical signaling is expected to remain more expensive than short-distance electrical signaling for quite some years to come, overall system cost would be reduced if dense electrical signaling could be used between circuit cards, thereby reducing the amount of optics in the system.
FIG. 1 depicts an exploded version of the mezzanine connector disclosed in copending parent case, U.S. patent application Ser. No. 12/986,132, to Thomas Cipolla, et al., the contents of which are incorporated by reference herein. The mezzanine connector of FIG. 1 depicts circuit card 1 and circuit card 2, a plurality of daughter circuit cards 2A, connector 3, comprising a header assembly 4, a top-base 6, a bottom-base 7 and a plurality of wafer assemblies 8. Header assembly 4 components comprise a header-base and a plurality of pin assemblies (not shown). Connector 3 is positioned orthogonally to circuit cards 1 and 2.
The present invention is an improvement over the Cipolla parent case noted above because the present invention provides for a tall mezzanine connector which does not utilize a header or other elements found in the prior art reference. The present invention therefore contains fewer separable interfaces and fewer subcomponents. It should therefore provide the desired function at lower cost and with higher reliability.
The present invention relates to a mezzanine connector which allows signals to leave both cards that are connected together from the middle of either card. Mezzanine connectors are known in the art, and have been used for applications similar to the present invention. The limitation of these existing connectors is their height.
The tallest mezzanine connectors presently available are on the order of 50 mm board-to-board (Tyco Micro-Strip connectors). This spatial dimension allows limited access to the space between circuit cards for placing other tall components, for example, daughter circuit cards in the space between the main circuit cards. Examples of daughter circuit cards are the VMEbus card, PCI card or memory card. These cards extend the functionality of the main or “mother card.”
The present invention allows limited access to the space between circuit cards for placing other tall components, for example, daughter circuit cards in the space between the main circuit cards. For future generation computers the ability to place daughter cards on circuit cards with the ability to stack another (or several) mother/daughter cards on the first one is highly desirable in order to minimize the length of signal nets thus maximizing the frequency the circuits can run.
The mezzanine connector of the present invention is an improvement in the art by virtue of its high speed, impedance-controlled signaling while retaining low connector cost; it allows large stack heights, so that multiple major system circuit boards can be stacked with a significant amount of tall electronics, power delivery and cooling on each system circuit board; and has a compliance feature which permits said large stack heights between system circuit boards and permits the system circuit boards themselves to be large in area.